1. Field of the Invention
The present invention relates to a driver circuit and a receiver circuit that can be applied to the transfer of digital information such as data in a semiconductor integrated circuit, and a technique for the transfer of digital signals.
2. Background
Signals handled in a semiconductor integrated circuit device are digital signals of pulse waveforms, and the transfer of signals is performed through metal wiring or the like formed in the same substrate. Since metal wiring is generally formed having a small cross-sectional area, wiring resistance is large, and coupling capacitance between wirings is large. Increase in wiring resistance and wiring capacitance increases the time constant of the pulse response, and causes pulse waveforms transferred through the wiring to become blunt. The blunt pulse may cause the clock of the signal transfer to become delayed, or the reliability of the signal transfer to decrease. Therefore, a driver circuit and a receiver circuit are used for ensuring the transfer of signals from the transmission side to the reception side. Since the signals received by the receiver circuit are of a blunt pulse form, and noise from adjacent metal wiring or the like is overlapped during the transfer of the signals, the pulse waveform is corrected by the receiver circuit. For the transfer of digital signals, the following methods are used.
FIG. 14 is a circuit diagram showing an example of conventional circuits for the transfer of digital signals. Two stages of inverters 101 and 102 configure the driver circuit 100 in the transmission side, which supplies input signals to the input terminal 103 of an inverter 101 of a first stage. The output of the second inverter 102 is from the output terminal 104 of the driver circuit, and signals that have been fully swung between the power supply voltage (e.g. 2.5 V) and the reference voltage (e.g. ground potential: 0 V) are outputted. The outputted signals are transferred through the signal line 105, and supplied to the input terminal 107 of the receiver circuit 106. The receiver circuit 106 is configured by a NOT circuit (inverter) 108 and a NAND circuit 109. The waveform of the input signal is corrected by the NOT circuit 108, and inputted to the NAND circuit 109. An action signal (ACT), i.e. a clock signal, is inputted to another input terminal of the NAND circuit 109. The output of the NAND circuit 109 is outputted from the output terminal 110 as the output of the receiver circuit 106.
FIG. 15 is a graph showing the simulated voltage waveforms at main parts of the circuit of FIG. 14. The waveform of the signal inputted to the input terminal 103 is shown by FIG. 15(a). The waveform of the signal after transferred through the signal line 105 and before inputted to the NOT circuit 108 is shown by FIG. 15(b). Bluntness is seen in this waveform. The output waveform of the NOT circuit 108 is shown by FIG. 15(c), and the blunt input waveform FIG. 15(b) has been corrected. The ACT signal is shown by FIG. 15(d), and the voltage waveform of the output terminal 110 is shown by FIG. 15(e). The ACT signal acts as the clock. The simulation conditions are: a line length of 9 mm for the signal line 105, a wiring load capacitance of 2.1 pF (of which load capacitance connected to the signal line is assumed as 500 fF), and a wiring resistance of 360 ohms.
FIG. 16 is a circuit diagram showing another example of a conventional digital signal transfer circuit. The driver circuit 120 is an n-type MISFET (n-type Metal Insulator Semiconductor Field Effect Transistor: hereafter an n-type MISFET is called NFET) 122 that discharges the electric charge pre-charged in the signal line 121, and the input signal is supplied to the input terminal 123, which is the gate of the NFET 122. The receiver circuit 124 is provided with an NFET 125, the gate of which is supplied with a reference voltage Vref, and a p-type MISFET (hereafter a p-type MISFET is called PFET) 126 for pre-charging is connected to the drain side of the NFET 125. An action signal ACT is supplied to the gate of the PFET 126, and when ACT is at Low level, the PFET 126 is turned ON, and the sense line 128 (the drain side of the NFET 125) is connected to the power supply voltage Vdd (e.g. 2.5V). At this time, the source side of the NFET 125 (signal line 121) is charged until the value becomes Vref minus the threshold voltage. The PFET 127 is an FET that has pull-up action for enhancing noise resistance when the sense line 128 is at High level while the ACT is at High level. The size of the PFET 127 is much smaller than the PFET 126.
FIG. 17 is a graph showing simulated operational waveforms of the circuit of FIG. 16. The input signal voltage at the input terminal 123 is shown by FIG. 17(a), the ACT signal is shown by FIG. 17(b), and the output signal voltage at the output terminal 130 is shown by FIG. 17(c). The line (d) shows the change in the voltage of the sense line 128, and the line (e) shows the change in the voltage of the signal line 121. Under the conditions where the ACT is at Low level, and the signal line 121 is pre-charged (t less than t1 in FIG. 17), the ACT is switched to High level (t=t1) to make the receiver circuit 124 read enabled. At this time, an input signal is inputted to the input terminal 123. When a High level is inputted (FIG. 17(a)), the NFET 122 is turned ON, and the voltage of the signal line 121 is lowered (line (e) in FIG. 17). The lowered voltage is transferred to the source of the NFET 125, and when the source potential is lowered to or below the voltage determined by Vref and the threshold voltage, the NFET 125 is turned ON, and the charge of the sense line 128 is rapidly transferred to the source side. And when the sense line 128 becomes Low level, a High level is outputted from the output terminal 130 connected through the inverter 129. At this time, since the PFET 127 is always ON, an ON current flows through the PFET 127; however, since the size of the PFET 127 is small, and the ON current is extracted by the NFET 122 as long as the NFET 122 is ON, the sense line 128 is kept at Low level.
In the method as described above, the digital signal is transferred from the driver circuit to the receiver circuit through the signal line.
However, with the increase in the density and performance of semiconductor integrated circuits in recent years, the number of devices integrated in a single semiconductor substrate (chip), and the length of wiring (signal lines) formed in the chip tend to increase. In the case of a DRAM (dynamic random access memory) for example, the length of wiring such as an address signal line becomes several. millimeters to several-tens of millimeters long, whereby parasitic capacitance (floating capacitance) and wiring resistance accompanying a signal line increase. Parasitic capacitance and wiring resistance accompanying wiring cause the form of pulses that pass through the wiring to be deformed, thereby causing the delay of signal transmission. Also, the parasitic capacitance and wiring resistance increases the power consumption due to wiring.
When a conventional transmission circuit as shown in FIG. 14 is used, the output 104 of the driver circuit 100 is driven by the source voltage of 2.5 V and the reference voltage of 0 V, and the amplitude can be as large as 2.5 V. Therefore, charge-discharge current increases due to wiring capacitance in the address signal line or the like with long wiring. For example, the result of the simulation of the average current consumption waveform obtained under the above-described simulation conditions, assuming that the input signal is 125 MHz and the operating frequency of the receiver circuit 106 is 250 MHz, is about 1 mA as FIG. 18 shows. If the total of address, bank, and command lines is assumed as 20, these consume 20 mA. Current consumption must be reduced when the design to add a heat dissipation device or the like are considered, and further improvement is absolutely necessary when use in mobile applications or the like are taken into account.
Although the realization of driving as low of a voltage amplitude as possible by a differential amplifier can be considered, common lines are required as well as signal lines, resulting in the disadvantage of the bus width being doubled. The application to products that require high density, such as DRAMs, cannot tolerate the increase in the wiring area.
When a conventional transmission circuit as shown in FIG. 16 is used, since the PFET 126 for pre-charging the signal line 121 is in the receiver side, there is a problem that the size of the PFET 126 cannot be increased. In the case of a DRAM, for example, the receiver circuit of the internal address line is provided in the vicinity of the memory array. Since the vicinity of the memory array is the region where the highest density is required, an increase in the size of the PFET 126 for pre-charging cannot be allowed in the circuit design. Therefore, there is another problem that the ON current of the PFET 126 cannot be increased, and a long time is required for pre-charging. Increase in the pre-charging time inhibits the improvement of operating frequency, or lowers the margin for operating frequency.
In the case of the transmission circuit of FIG. 16, after an input signal has been sensed, the next signal cannot be read accurately unless the input 123 is once reset to a Low level and the signal line 121 is pre-charged regardless of the value of the next signal. Assuming that an input signal of a Low level is inputted after an input signal of a High level, the Low level is erroneously recognized as a High level unless the signal line 121 is pre-charged. Therefore, even if a High level is continuously inputted as in the refreshing operation of a DRAM, the pre-charging operation is performed in every cycle, and the pre-charging operation is wastefully repeated. As a result, electric power consumed by pre-charging is wasted. In this type of transmission circuit, since resetting is required every cycle, the timing control circuit for generating input signals and pre-charging pulses is also required, and electric power consumed by such a control circuit increases.
Furthermore, in the case of the transmission circuit of FIG. 16, the PFET 126 for pre-charging is in an OFF state when the circuit is in a read-enable operating condition, and the signal line 121 is in the nearly Hi-Z state (high-impedance state) at this time. That is, even if the PFET 127 is in the ON state, the PFET 127 has a small ability to supply electric current, which is not sufficient to drive the signal line 121. In such a state, the transmission circuit is easily affected by noise, for example, due to change in voltage of adjacent signal lines, and such noise may cause erroneous operations.
A driver circuit (20, 50) of the present invention which comprises an inverter comprising a first transistor (21) of a first type and a second transistor (23) of a second type, and a third transistor (22) of a second type provided between the first transistor (21) and the second transistor (23), to which a second voltage (Vref) lower than a first voltage (Vdd) that drives the circuit is supplied at the control input terminal thereof.
According to such a driver circuit, the output voltage can be limited by the second voltage (Vref) impressed on the gate of the third transistor (22), while driving the input signal with the inverter. Since the amplitude of signal waveforms supplied to the signal line is small, the charge/discharge current consumed by the signal line can be minimized, and power consumption can be reduced.
Also, according to such a driver circuit, current for charging the signal line (30) through the first transistor (21) and the third transistor (22) can be transmitted. Therefore, when the charge transfer system is adopted, there is no need to provide an FET for pre-charging in the receiver circuit. As a result, current conventionally required for pre-charging can be eliminated. The voltage impressed in the signal line (30) can be adjusted to be lower than the first voltage (Vdd) by the second voltage (Vref) impressed on the gate of the third transistor (22). As a result, current consumption (power consumption) can also be reduced by lowering the charge-up voltage of the signal line (30).
Here, the threshold voltage of the third transistor (22) can be lower than the threshold voltage of the first or second transistor (21, 23).
Furthermore, FIG. 2 shows a fourth transistor (24) that is connected to the third transistor (22) in parallel can be provided. To the gate of the fourth transistor can be impressed a signal that is turned ON for a period shorter than the input signal or the clock period of the driver circuit when a signal to turn the first transistor (21) ON is impressed to the input (DIN) of the inverter, whereby the rising time of the output signal from the driver circuit can be shortened.
Also shown in FIG. 2 is a receiver circuit (40) of the present invention which comprises a fifth transistor (41) of a first type and a sixth transistor (42) of a second type that are complementarily composed and supplied with a first voltage (Vdd) for driving the circuit from a terminal, and with a clock signal (ACT) from the control input terminal; a seventh transistor (43) of a second type, in which a terminal thereof is connected to another terminal of the fifth and sixth transistors (41, 42), and the other terminal thereof is connected to a reference voltage (GND:ground voltage), and an input signal (RIN) of a voltage lower than the first voltage (Vdd) is supplied to the control input terminal; and an inverter (45) that inverts and outputs the output of the dynamic NAND circuit composed of the fifth, sixth, and seventh transistors (41, 42, 43).
According to such a receiver circuit, a small signal pulse can be received by a dynamic NAND circuit that functions as a level converter, and the converted level (the output of the NAND circuit) can be driven by the inverter circuit of the subsequent stage. Therefore, a signal having a small amplitude in the driving voltage level can be sensed with a high sensitivity.
Here, the threshold voltage of the seventh transistor (43) can be lower than the threshold voltage of the fifth transistor (41). By inputting a signal to this gate using the seventh transistor (43) of low threshold voltage, the receiver circuit can handle a signal of small amplitude. Also by connecting the source of the seventh transistor (43) to a reference voltage (ground voltage), the occurrence of the body effect of the seventh transistor (43) on evaluating (ACT=High) can be inhibited. If the body effect occurs, the threshold voltage of the FET is elevated, delaying the timing of turning ON. According to the present invention, however, since the body effect is limited, the delay of the timing of turning ON does not occur, and the response time of the receiver circuit (40) can be shortened.
The sixth transistor (42) can be a transistor with a low threshold voltage. Thus, the voltage when the output of the dynamic NAND is in a Low level can approach the reference voltage, and a degradation in receiver sensitivity can be prevented. That is, the receiver circuit (40) can eliminate the need for correcting the waveforms, and can shift the level of the input signal (RIN) while simultaneously receiving the input signal (RIN). Furthermore, when a plurality of signal lines (30) are present, as address lines, the skew of each address signal can be equalized by adjusting the operation of each receiver at the same time of receiving, which realizes a signal transmission circuit of low power consumption suitable for a synchronized circuit or pipe-line operation.
FIG. 8 shows another receiver circuit (60) of the present invention which comprises an eighth transistor (62) that has a terminal connected to the signal line (30), a control input terminal connected to the second voltage (Vref), and another terminal connected to the output stage, for sensing change in the voltage of the signal line (30) from the charge transfer between the terminals; and a ninth transistor (61) provided between the signal line (30) and the eighth transistor (62), for separating the signal line (30) from the eighth transistor (62) while change in the voltage of the signal line (30) is not sensed.
Such a receiver circuit (60) can make the ninth transistor (61) operate as a selector, and can separate the signal line (30) from the receiver circuit, thereby allowing the signal line (30) to be charged from the driver circuit. Therefore, an FET for pre-charging is not required in the receiver circuit (60), and the occupied device area of the receiver circuit can be reduced. The reduction of the occupied device area increases circuit design flexibility. Also, the size of the conventional pre-charging circuit can be reduced, and the load capacitance to the sense line can be decreased, thus improving the sensitivity of the receiver circuit (60).
The threshold voltage of the ninth transistor (61) can be lower than the threshold voltage of the eighth transistor (62), whereby the response to sensing can be improved. The output stage of the receiver circuit can be provided with a latch circuit, which facilitates the timing design of the subsequent stage circuit receiving the output of the receiver.
A semiconductor integrated circuit device can be configured by using the above-described driver circuit (20, 50) and receiver circuit (40, 60). When the semiconductor integrated circuit device using the receiver circuit (60) is used, there is no need for resetting the input signal (DIN) in each cycle. This eliminates the need for changing the voltage of the signal line when there is no change in the input signal as in refreshing the DRAM, and saves electric power required by conventional pre-charging operations. Also, no pulse generating circuit of input signals is required, and power consumed by the pulse generating circuit can be saved. The margin for the timing control of operation signals (ACT) and inputs (DIN) is also increased. Furthermore, since the Hi-Z period when the signal line is released from any voltage can be eliminated, resistance to noise can be improved, and stable circuit operation can be realized.
The driver circuit (20, 50), the receiver circuit (40, 60), and the signal line (30) may be formed in the same semiconductor or insulator substrate, and a plurality of signal lines (30) may be formed in parallel apart from each other. Since the semiconductor integrated circuit of the present invention has a low sensitivity to noise, it is especially effective to apply the semiconductor integrated circuit of the present invention to highly integrated semiconductor integrated circuits in which a plurality of signal lines are formed in parallel.
An aspect of the present invention is to decrease the electric power consumed by digital signal transmission circuits.
Another aspect of the present invention is to improve the operational speed of digital signal transmission circuits.
Still another aspect of the present invention is to improve the noise resistance of digital signal transmission circuits.
Yet another aspect of the present invention is to improve the performance of digital signal transmission circuits, and to improve the reliability and the performance of semiconductor integrated circuits.